The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2008

Filed:

Nov. 05, 2007
Applicants:

Mitsuru Kaneda, Tokyo, JP;

Hideki Takahashi, Tokyo, JP;

Inventors:

Mitsuru Kaneda, Tokyo, JP;

Hideki Takahashi, Tokyo, JP;

Assignee:

Mitsubishi Denki Kabushiki Kaisha, Chiyoda-Ku, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 21/338 (2006.01); H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is formed on the collector region. Also, at least one pair of isolation regions of the second conductivity type are formed extending from the upper surface of the semiconductor substrate to the collector layer for defining a drift region of the first conductivity type, in conjunction with the collector region. A base region of the second conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the drift region, and an emitter region of the first conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the base region. A gate electrode is formed opposing to the base region via an insulating layer. An emitter electrode is formed on the emitter region. The collector layer has thickness in the range between 17 μm to 50 μm.


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