The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2008
Filed:
Aug. 11, 2006
Bart Reynolds, Seattle, WA (US);
Keith R. Bean, Greeley, CO (US);
Daniel P. Kirkwood, Denver, CO (US);
James F. Barei, Seattle, WA (US);
Benjamin D. Ralston, Bellevue, WA (US);
Bart Reynolds, Seattle, WA (US);
Keith R. Bean, Greeley, CO (US);
Daniel P. Kirkwood, Denver, CO (US);
James F. Barei, Seattle, WA (US);
Benjamin D. Ralston, Bellevue, WA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A processor-implemented method is provided for determining first and second indices of cell instances of a configuration memory cell of a tile module of a programmable logic device (PLD) design. A netlist is input that describes the PLD design and includes the cell instances of the configuration memory cell. An identification of the tile module is input. Characterization data is input for each configuration memory cell specifying address and data input pins. Characterization data is input for each configuration control module specifying a first ordered set of address output pins and a second ordered set of data output pins. For each of the cell instances, the first index of an address output pin in the first ordered set and the second index of a data output pin in the second ordered set are determined and a specification is output of the cell instance and the first and second indices.