The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2008
Filed:
Aug. 11, 2006
Bart Reynolds, Seattle, WA (US);
Keith R. Bean, Greeley, CO (US);
Daniel P. Kirkwood, Denver, CO (US);
James F. Barei, Seattle, WA (US);
Benjamin D. Ralston, Bellevue, WA (US);
Bart Reynolds, Seattle, WA (US);
Keith R. Bean, Greeley, CO (US);
Daniel P. Kirkwood, Denver, CO (US);
James F. Barei, Seattle, WA (US);
Benjamin D. Ralston, Bellevue, WA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A processor-implemented method is provided for determining reachable pins functionally connected to a network of a netlist that describes a programmable logic device (PLD) design. A netlist and an identification of the network in the netlist are input. Characterization data is input for one or more repeater modules that specify a first set of functionally connected pins of the repeater module. A second set is initialized with the pins of the network. For each pin in the second set that is one of the functionally connected pins of a first set, an additional pin may be added to the second set for each of the pins of a network for each of the functionally connected pins. The adding is repeated for each additional pin added to the second set. A specification of the pins from the second set is output as the reachable pins.