The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2008
Filed:
Mar. 14, 2006
Arya Reza Behzad, Poway, CA (US);
Matthew Vernon Kaufmann, Morgan Hill, CA (US);
Malcolm Macintosh, Escondido, CA (US);
Jacob Jude Rael, Lake Forest, CA (US);
Henry K. Chen, Irvine, CA (US);
Arya Reza Behzad, Poway, CA (US);
Matthew Vernon Kaufmann, Morgan Hill, CA (US);
Malcolm MacIntosh, Escondido, CA (US);
Jacob Jude Rael, Lake Forest, CA (US);
Henry K. Chen, Irvine, CA (US);
Broadcom Corporation, Irvine, CA (US);
Abstract
Forming a wafer level chip scale flip chip package includes determining isolation requirements of an integrated circuit formed in a semi conductive substrate from package signal connections of the wafer level chip scale flip chip package. Operation may further include, based upon the integrated circuit characteristics, selecting a thickness of at least one dielectric layer isolating a top metal layer of the integrated circuit from the package signal connections of the wafer level chip scale flip chip package, determining a minimum pitch of the package signal connections of the wafer level chip scale flip chip package, and determining a maximum lateral distance from the signal pad to a servicing package signal connection of the wafer level chip scale flip chip package and determining a position of the servicing package signal connection of the wafer level chip scale flip chip package based upon the maximum lateral distance.