The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2008

Filed:

Jan. 05, 2005
Applicants:

Anand V. Kamannavar, Cincinnati, OH (US);

Nathan Dirk Zelle, Dallas, TX (US);

Bradley Forrest Bass, Carrollton, TX (US);

Sahir Shiraz Hoda, Plano, TX (US);

Erich Matthew Gens, Allen, TX (US);

Inventors:

Anand V. Kamannavar, Cincinnati, OH (US);

Nathan Dirk Zelle, Dallas, TX (US);

Bradley Forrest Bass, Carrollton, TX (US);

Sahir Shiraz Hoda, Plano, TX (US);

Erich Matthew Gens, Allen, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification command to verify a portion of a hardware design of a device under test. The error verification object is compiled in accordance with data provided by an error scripting module. The error scripting module has access to hardware-specific data corresponding to the hardware design of the device under test. The compiled object is sent to the device under test and a response to the compiled object is received from the device under test. The received response from the device under test is parsed in accordance with data provided by the error scripting module.


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