The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2008
Filed:
Nov. 01, 2006
Shih-chen Wang, Taipei, TW;
Hsin-ming Chen, Tainan Hsien, TW;
Chun-hung LU, Yun-Lin County, TW;
Ming-chou Ho, Hsin-Chu, TW;
Shih-jye Shen, Hsin-Chu, TW;
Ching-hsiang Hsu, Hsin-Chu, TW;
Shih-Chen Wang, Taipei, TW;
Hsin-Ming Chen, Tainan Hsien, TW;
Chun-Hung Lu, Yun-Lin County, TW;
Ming-Chou Ho, Hsin-Chu, TW;
Shih-Jye Shen, Hsin-Chu, TW;
Ching-Hsiang Hsu, Hsin-Chu, TW;
eMemory Technology Inc., Science Park, Hsinchu, TW;
Abstract
A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a dielectric stack layer on sidewalls of the gate, a source doping region and a drain doping region. The dielectric stack layer includes a first oxide layer deposited on the sidewalls of the gate and extends to the ion well, and a silicon nitride layer formed on the first oxide layer. The silicon nitride layer functions as a charge-trapping layer.