The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2008

Filed:

Apr. 11, 2005
Applicants:

Won-jun Lee, Seoul, KR;

Tae-hyun Kim, Gyeonggi-do, KR;

Yong-sun Ko, Gyeonggi-do, KR;

Kyung-hyun Kim, Seoul, KR;

Byoung-moon Yoon, Gyeonggi-do, KR;

Ji-hong Kim, Seoul, KR;

Inventors:

Won-Jun Lee, Seoul, KR;

Tae-Hyun Kim, Gyeonggi-do, KR;

Yong-Sun Ko, Gyeonggi-do, KR;

Kyung-Hyun Kim, Seoul, KR;

Byoung-Moon Yoon, Gyeonggi-do, KR;

Ji-Hong Kim, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 Å to about 200 Å. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.


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