The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2008

Filed:

Apr. 23, 2003
Applicants:

Manu Chopra, New Delhi, IN;

Xiaoqun Du, New Providence, NJ (US);

Alok Jain, New Delhi, IN;

Robert P. Kurshan, New York, NY (US);

Franz Erich Marschner, Ellicott City, MD (US);

Kavita Ravi, Chatham, NJ (US);

Inventors:

Manu Chopra, New Delhi, IN;

Xiaoqun Du, New Providence, NJ (US);

Alok Jain, New Delhi, IN;

Robert P. Kurshan, New York, NY (US);

Franz Erich Marschner, Ellicott City, MD (US);

Kavita Ravi, Chatham, NJ (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and system for verifying circuit designs through propagation of assertions within a circuit design. In an embodiment, a plurality of provided assertions a circuit design are propagated within the circuit design. The circuit design is then verified using at least one of the propagated assertions as an assumption.


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