The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2008

Filed:

Sep. 20, 2005
Applicants:

Tiao-hua Kuo, San Jose, CA (US);

Nancy Leong, Sunnyvale, CA (US);

Nian Yang, Mountain View, CA (US);

Guowei Wang, Cupertino, CA (US);

Aaron Lee, Mountain View, CA (US);

Sachit Chandra, Sunnyvale, CA (US);

Michael A. Vanbuskirk, Saratoga, CA (US);

Johnny Chen, Sunnyvale, CA (US);

Darlene Hamilton, San Jose, CA (US);

Binh Quang Le, San Jose, CA (US);

Inventors:

Tiao-Hua Kuo, San Jose, CA (US);

Nancy Leong, Sunnyvale, CA (US);

Nian Yang, Mountain View, CA (US);

Guowei Wang, Cupertino, CA (US);

Aaron Lee, Mountain View, CA (US);

Sachit Chandra, Sunnyvale, CA (US);

Michael A. VanBuskirk, Saratoga, CA (US);

Johnny Chen, Sunnyvale, CA (US);

Darlene Hamilton, San Jose, CA (US);

Binh Quang Le, San Jose, CA (US);

Assignee:

Spansion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.


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