The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2008
Filed:
Dec. 03, 2004
Kengo Imagawa, Fujisawa, JP;
Masami Makuuchi, Yokohama, JP;
Norio Chujo, Tokyo, JP;
Ritsuro Orihashi, Tokyo, JP;
Yoshitomo Arai, Ohme, JP;
Kengo Imagawa, Fujisawa, JP;
Masami Makuuchi, Yokohama, JP;
Norio Chujo, Tokyo, JP;
Ritsuro Orihashi, Tokyo, JP;
Yoshitomo Arai, Ohme, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A problem, which one of the inventions included in the present application solves, is to provide a semiconductor device that can simultaneously test a plurality of output pins by less channels of a semiconductor test equipment in number than the integrated output pins of the semiconductor device. Representative one of the inventions has such a configuration that an LCD driver, which is the semiconductor device having a function of driving a gate line of a liquid crystal display panel, comprises: an exclusive-OR circuit for inverting polarities of positive and negative voltages for driving the gate line; a tri-state type inverter circuit capable of changing and controlling, to a high-impedance state, an output circuit for driving the gate line; and at least one of test control terminals TEST for controlling the exclusive-OR circuit and the tri-state type inverter circuit. When a test is conducted, only one terminal of the gate output outputs a positive voltage VGH or negative voltage VGL and the other terminal is set to a high-impedance state, whereby the plurality of gate outputs are simultaneously tested.