The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2008

Filed:

Dec. 21, 2006
Applicants:

William B. Andrews, Macungie, PA (US);

Mou C. Lin, High Bridge, NJ (US);

John A. Schadt, Bethlehem, PA (US);

Inventors:

William B. Andrews, Macungie, PA (US);

Mou C. Lin, High Bridge, NJ (US);

John A. Schadt, Bethlehem, PA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
Abstract

An improved output buffer having a digital output slew control and compensation for manufacturing process variations. Output slewing is accomplished by sequencing digital drive signals to paralleled output transistors. In one embodiment, a pre-driver sequences the drive signals by using the propagation delays of serially coupled digital logic gates to reduce power supply droop and/or ground bounce. The output transistors are turned off substantially simultaneously to avoid undesirable power supply DC current flow when the output buffer changes state. Programmably configuring the number of paralleled transistors that may be turned on at any given time allows a user to compensate for manufacturing process variations and determine the output impedance/drive capacity of the buffer.


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