The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2008

Filed:

Feb. 22, 2006
Applicants:

Jong-wook Lee, Yongin-si, KR;

Deok-hyung Lee, Yongin-si, KR;

Min-gu Kang, Namyangju-si, KR;

Yu-gyun Shin, Seongnam-si, KR;

Inventors:

Jong-Wook Lee, Yongin-si, KR;

Deok-Hyung Lee, Yongin-si, KR;

Min-Gu Kang, Namyangju-si, KR;

Yu-Gyun Shin, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
Abstract

A fin type field effect transistor includes a semiconductor substrate, an active fin, a first hard mask layer pattern, a gate insulation layer pattern, a first conductive layer pattern, and source/drain regions. The active fin includes a semiconductor material and is formed on the substrate and extends in a direction away from a major surface of the substrate. The first hard mask layer pattern is formed on a distal surface of the active fin from the substrate. The gate insulation layer is formed on a sidewall portion of the active fin. The first conductive layer pattern includes a metal silicide and is formed on surfaces of the substrate and the gate insulation layer pattern, and on a sidewall of the first hard mask pattern. The source/drain regions are formed in the active fin on opposite sides of the first conductive layer pattern.


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