The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2008
Filed:
Jun. 15, 2006
Karl R. Amundson, Cambridge, MA (US);
Guy M. Danner, Somerville, MA (US);
Gregg M. Duthaler, Needham, MA (US);
Peter T. Kazlas, Sudbury, MA (US);
Yu Chen, Milpitas, CA (US);
Kevin L. Denis, Bowie, MD (US);
Nathan R. Kane, Arlington, MA (US);
Andrew P. Ritenour, Arlington, MA (US);
Karl R. Amundson, Cambridge, MA (US);
Guy M. Danner, Somerville, MA (US);
Gregg M. Duthaler, Needham, MA (US);
Peter T. Kazlas, Sudbury, MA (US);
Yu Chen, Milpitas, CA (US);
Kevin L. Denis, Bowie, MD (US);
Nathan R. Kane, Arlington, MA (US);
Andrew P. Ritenour, Arlington, MA (US);
E Ink Corporation, Cambridge, MA (US);
Abstract
A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors. The invention also provides a process for forming a diode on a substrate by depositing on the substrate a first conductive layer, and a second patterned conductive layer and a patterned dielectric layer over parts of the first conductive layer, and etching the first conductive layer using the second conductive layer and dielectric layer as an etch mask. Finally, the invention provides a process for driving an impulse-sensitive electro-optic display.