The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2008

Filed:

Dec. 28, 2006
Applicants:

Yasuhiro Takeda, Ogaki, JP;

Mitsuaki Morigami, Ogaki, JP;

Satoru Shimada, Hashima, JP;

Kazuhiro Yoshitake, Oota, JP;

Shuichi Kikuchi, Gunma-ken, JP;

Seiji Otake, Kumagaya, JP;

Toshiyuki Ohkoda, Gunma-ken, JP;

Inventors:

Yasuhiro Takeda, Ogaki, JP;

Mitsuaki Morigami, Ogaki, JP;

Satoru Shimada, Hashima, JP;

Kazuhiro Yoshitake, Oota, JP;

Shuichi Kikuchi, Gunma-ken, JP;

Seiji Otake, Kumagaya, JP;

Toshiyuki Ohkoda, Gunma-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.


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