The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2008

Filed:

Aug. 18, 2005
Applicants:

Joseph K. Fauty, Mesa, AZ (US);

James P. Letterman, Jr., Mesa, AZ (US);

Denise Thienpont, Scottsdale, AZ (US);

Inventors:

Joseph K. Fauty, Mesa, AZ (US);

James P. Letterman, Jr., Mesa, AZ (US);

Denise Thienpont, Scottsdale, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.


Find Patent Forward Citations

Fauty, Joseph. (2008). Encapsulated chip scale package having flip-chip on lead frame structure and method (U.S. Patent No. 7439100). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7439100

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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