The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2008
Filed:
Aug. 03, 2005
Naoki Kumagai, Nagano, JP;
Yuuichi Harada, Nagano, JP;
Hiroshi Kanemaru, Nagano, JP;
Yoshihiro Ikura, Nagano, JP;
Ryuu Saitou, Nagano, JP;
Naoki Kumagai, Nagano, JP;
Yuuichi Harada, Nagano, JP;
Hiroshi Kanemaru, Nagano, JP;
Yoshihiro Ikura, Nagano, JP;
Ryuu Saitou, Nagano, JP;
Abstract
A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n-type drain region in the first n-type well, a p-type well in the first n-type well, an n-type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n-type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.