The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2008
Filed:
May. 31, 2006
Brian A. Winstead, Austin, TX (US);
Omar Zia, Austin, TX (US);
Mariam G. Sadaka, Austin, TX (US);
Marius K. Orlowski, Austin, TX (US);
Brian A. Winstead, Austin, TX (US);
Omar Zia, Austin, TX (US);
Mariam G. Sadaka, Austin, TX (US);
Marius K. Orlowski, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor process and apparatus provide a planarized hybrid substrate () by exposing a buried oxide layer () in a first area (), selectively etching the buried oxide layer () to expose a first semiconductor layer () in a second smaller seed area (), and then epitaxially growing a first epitaxial semiconductor material from the seed area () of the first semiconductor layer () that fills the second trench opening () and grows laterally over the exposed insulator layer () to fill at least part of the first trench opening (), thereby forming a first epitaxial semiconductor layer () that is electrically isolated from the second semiconductor layer (). By forming a first SOI transistor device () over a first SOI layer () using deposited (100) silicon and forming first SOI transistor () over an epitaxially grown (110) silicon layer (), a high performance CMOS device is obtained.