The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7432189 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 07, 2008

Filed:

Nov. 30, 2005
Applicants:

S. M. Reza Sadjadi, Saratoga, CA (US);

Zhi-song Huang, Fremont, CA (US);

Inventors:

S. M. Reza Sadjadi, Saratoga, CA (US);

Zhi-Song Huang, Fremont, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.


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Reza Sadjadi, S.. (2008). Device with self aligned gaps for capacitance reduction (U.S. Patent No. 7432189). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7432189

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