The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2008
Filed:
May. 25, 2006
Fu-chiung Cheng, Taipei, TW;
Shu-ming Chang, Taipei, TW;
Jian-yi Chen, Taipei, TW;
Chieh-ju Wang, Taipei, TW;
Chin-tai Chou, Taipei, TW;
Nian-zhi Huang, Taipei, TW;
Chi-huam Shieh, Taipei, TW;
Ping-yun Wang, Taipei, TW;
Li-kai Chang, Taipei, TW;
Fu-Chiung Cheng, Taipei, TW;
Shu-Ming Chang, Taipei, TW;
Jian-Yi Chen, Taipei, TW;
Chieh-Ju Wang, Taipei, TW;
Chin-Tai Chou, Taipei, TW;
Nian-Zhi Huang, Taipei, TW;
Chi-Huam Shieh, Taipei, TW;
Ping-Yun Wang, Taipei, TW;
Li-Kai Chang, Taipei, TW;
Tatung Company, Taipei, TW;
Abstract
An HCG to HDL translation method, which can automatically generate VHDL codes. The method reads a hardware component graph (HCG) to find a start node and obtain a corresponding hardware component subgraph of the start node, analyzes all information of the start node to thereby add input and output components and generate a VHDL entity, determines types on all nodes of the hardware component, graph to thereby generate corresponding VHDL components and write associated information in a VHDL architecture, generates corresponding signal connections of VHDL components in accordance with edges of the hardware component graph, and outputs the VHDL entity and architecture to a file in a text form.