The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7430134 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 30, 2008

Filed:

Feb. 20, 2007
Applicants:

Yasuhisa Takeyama, Yokohama, JP;

Nobuaki Otsuka, Komae, JP;

Osamu Hirabayashi, Tokyo, JP;

Inventors:

Yasuhisa Takeyama, Yokohama, JP;

Nobuaki Otsuka, Komae, JP;

Osamu Hirabayashi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is an SRAM including a latch circuit, first and second write transfer gates, first and second write buffer transistors, read driver transistor, and read transfer gate. A write path is formed by connecting first and second write transfer gates and first and second write buffer transistors to the latch circuit which stores data and the path is controlled by use of a word line and data write bit lines. Further, a read path is formed by connecting a read driver transistor and read transfer gate to the latch circuit and the path is controlled by use of the word line, read bit line and data of the latch circuit.


Find Patent Forward Citations

Takeyama, Yasuhisa. (2008). Memory cell structure of sram (U.S. Patent No. 7430134). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7430134

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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