The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2008
Filed:
Sep. 30, 2005
Paul Ying-fung Wu, Saratoga, CA (US);
Soon-shin Chee, Sunnyvale, CA (US);
Steven H. C. Hsieh, Cupertino, CA (US);
Paul Ying-Fung Wu, Saratoga, CA (US);
Soon-Shin Chee, Sunnyvale, CA (US);
Steven H. C. Hsieh, Cupertino, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.