The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2008
Filed:
Dec. 31, 2002
Joel R. Phillips, Sunnyvale, CA (US);
Baolin Yang, Fremont, CA (US);
Joel R. Phillips, Sunnyvale, CA (US);
Baolin Yang, Fremont, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method, computer program product, and apparatus for simulating circuits. The method comprises modeling a circuit with an appropriate system of equations, partitioning a time interval on which the system of equations is defined, producing an interpolating polynomial on the time interval, and applying a two tiered iterative approach to solve the system of equations. The approach begins by decomposing a candidate solution vector into its time domain and frequency domain components. The Fourier transform is applied to the frequency domain components and time domain methods are applied to both the time domain components and the Fourier transformed frequency domain components to generate the solution to the original system of equations. Newton's method can be used in combination with a Krylov iterative subspace solver to perform the two-tiered iteration. The computer program product and the apparatus implement the method of simulating circuits.