The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2008

Filed:

Jul. 21, 2005
Applicants:

Andrew Strachan, Santa Clara, CA (US);

Natalia Lavrovskaya, Sunnyvale, CA (US);

Saurabh Desai, Fremont, CA (US);

Roozbeh Parsa, San Jose, CA (US);

Yuri Mirgorodski, Sunnyvale, CA (US);

Inventors:

Andrew Strachan, Santa Clara, CA (US);

Natalia Lavrovskaya, Sunnyvale, CA (US);

Saurabh Desai, Fremont, CA (US);

Roozbeh Parsa, San Jose, CA (US);

Yuri Mirgorodski, Sunnyvale, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

A biased conductive plate is provided over an NVM cell structure to overcome data retention charge loss due to the presence of dielectric films that are conductive at higher temperatures. The biased conductive plate is preferably formed from the lowest metal layer in the fabrication process flow, but any biased conductive layer can be used.


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Strachan, Andrew. (2008). Eeprom structure with improved data retention utilizing biased metal plate and conductive layer exclusion (U.S. Patent No. 7425741). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7425741

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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