The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2008
Filed:
Apr. 01, 2003
Edwin A. Harcourt, Townsend, MA (US);
Koushik Roy, Tyngsboro, MA (US);
Doug Dunlop, Potomac, MD (US);
Stuart C. Rae, Jefferson, MA (US);
Tuay-ling K. Lang, Boxborough, MA (US);
Andrew Wilmot, Carlisle, MA (US);
Bishnupriya Bhattacharya, Sunnyvale, CA (US);
Robert Shur, Los Altos, CA (US);
Edwin A. Harcourt, Townsend, MA (US);
Koushik Roy, Tyngsboro, MA (US);
Doug Dunlop, Potomac, MD (US);
Stuart C. Rae, Jefferson, MA (US);
Tuay-Ling K. Lang, Boxborough, MA (US);
Andrew Wilmot, Carlisle, MA (US);
Bishnupriya Bhattacharya, Sunnyvale, CA (US);
Robert Shur, Los Altos, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method for simulation of mixed-language circuit designs is disclosed. In one embodiment, an object-oriented language module is natively instantiated within a hardware description language based design. In another embodiment, a hardware description language module is natively instantiated within an object-oriented language based design. A system for simulation of mixed-language circuit designs is also disclosed. In one embodiment, a simulator is configured to natively manipulate an object-oriented language module within a hardware description language based design. In another embodiment, a simulator is configured to natively manipulate a hardware description language module within an object-oriented language based design.