The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2008
Filed:
Apr. 03, 2007
Ching Chung Lin, Banciao, TW;
Ken Hui Chen, Dali, TW;
Nai Ping Kuo, Hsinchu, TW;
Han Sung Chen, Hsinchu, TW;
Chun Hsiung Hung, Hsinchu, TW;
Wen Yi Hsieh, Seagun Township, TW;
Ching Chung Lin, Banciao, TW;
Ken Hui Chen, Dali, TW;
Nai Ping Kuo, Hsinchu, TW;
Han Sung Chen, Hsinchu, TW;
Chun Hsiung Hung, Hsinchu, TW;
Wen Yi Hsieh, Seagun Township, TW;
Macronix International Co., Ltd., Hsinchu, TW;
Abstract
A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride read-only memory array. If an operation requests erasing on the left side of nitride read-only memory cells, a positive voltage is supplied from an internal power supply to the left side for each of the nitride read-only memory cells, and the right side for each of the nitride read-only memory cells is discharged to a common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.