The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2008

Filed:

Aug. 18, 2005
Applicants:

Takeshi Nogami, Hopewell Junction, NY (US);

Kensaku Ida, Wappingers Falls, NY (US);

Inventors:

Takeshi Nogami, Hopewell Junction, NY (US);

Kensaku Ida, Wappingers Falls, NY (US);

Assignees:

Sony Corporation, Tokyo, JP;

Sony Electronics Inc., Park Ridge, NJ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Next, first and second dielectric layers are formed on the first and second spacer layers, respectively, such that each of the first and second dielectric layers is separated by one of the spacer layers. The first and second dielectric layers each include a first and second dielectric component. The second dielectric component is a sacrificial dielectric material. At least a portion of the second dielectric component is removed to thereby form voids in the first and second dielectric layers. At least a portion of the sacrificial dielectric material in the first and second spacer layers is also removed to thereby form voids in the first and/or second spacer layers.


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