The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2008
Filed:
Dec. 14, 2005
Giuseppe Curello, Portland, OR (US);
Hemant V. Deshpande, Beaverton, OR (US);
Sunit Tyagi, Portland, OR (US);
Mark Bohr, Aloha, OR (US);
Giuseppe Curello, Portland, OR (US);
Hemant V. Deshpande, Beaverton, OR (US);
Sunit Tyagi, Portland, OR (US);
Mark Bohr, Aloha, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.