The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2008
Filed:
Apr. 07, 2005
Jae-hong Kim, Cheonan-si, KR;
Heui-seog Kim, Cheonan-si, KR;
Wha-su Sin, Cheonan-si, KR;
Jong-keun Jeon, Cheonan-si, KR;
Jae-Hong Kim, Cheonan-si, KR;
Heui-Seog Kim, Cheonan-si, KR;
Wha-Su Sin, Cheonan-si, KR;
Jong-Keun Jeon, Cheonan-si, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A package stack may include a first package and a second package. The first package may have an IC chip with an active surface and a back surface. The active surface may be connected to a first major surface of a first circuit substrate. The second package may include a second IC chip with an active surface and a back surface. The back surface of the second IC chip may be attached to a first major surface of a second circuit substrate and the active surface of the second IC chip may be electrically connected to the first major surface of the second circuit substrate. The first package may be stacked on the second package so that the active surface of the second package may be electrically connected to a second major surface of the first circuit substrate of the first package. A method may involve providing a first package having a first IC chip and a first circuit substrate and providing a second package having a second IC chip and a second circuit substrate. The first and the second packages may be stacked so that the active surface of the second IC may face and be electrically connected to a major surface of the first circuit substrate.