The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2008

Filed:

Jan. 20, 2006
Applicants:

Kuo-ming Wu, Hsinchu, TW;

Jian-hsing Lee, Hsin-Chu, TW;

Yi-chun Lin, Hsinchu, TW;

Chi-chih Chen, Dounan Township, Yunlin County, TW;

Inventors:

Kuo-Ming Wu, Hsinchu, TW;

Jian-Hsing Lee, Hsin-Chu, TW;

Yi-Chun Lin, Hsinchu, TW;

Chi-Chih Chen, Dounan Township, Yunlin County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.


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