The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2008
Filed:
Dec. 29, 2006
Jin-ho Kim, Gyeonggi-do, KR;
Jae-kwan Park, Gyeonggi-do, KR;
Dong-hwa Kwak, Gyeonggi-do, KR;
Su-jin Ahn, Seoul, KR;
Yoon-moon Park, Seoul, KR;
Jue-hwang Sim, Seoul, KR;
Jang-ho Park, Gyeonggi-do, KR;
Sang-yong Park, Gyeonggi-do, KR;
Jin-Ho Kim, Gyeonggi-do, KR;
Jae-Kwan Park, Gyeonggi-do, KR;
Dong-Hwa Kwak, Gyeonggi-do, KR;
Su-Jin Ahn, Seoul, KR;
Yoon-Moon Park, Seoul, KR;
Jue-Hwang Sim, Seoul, KR;
Jang-Ho Park, Gyeonggi-do, KR;
Sang-Yong Park, Gyeonggi-do, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with a second pitch in the second region that are alternately arranged with the first patterns, forming a space insulating layer that covers the first and second patterns and comprises gap regions that are alternately arranged with the first patterns so as to correspond with the second patterns, forming third patterns that correspond to the second patterns in the gap regions, respectively, etching the space insulating layer between the first and second patterns and between the first and third patterns, such that the space insulating layer remains between the second patterns and the third patterns, and etching the lower layer using the first, second, and third patterns and the remaining space insulating layer between the second and third patterns as an etching mask.