The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2008

Filed:

Apr. 10, 2007
Applicants:

Kikuko Sugimae, Yokohama, JP;

Hiroyuki Kutsukake, Yokohama, JP;

Masayuki Ichige, Yokohama, JP;

Michiharu Matsui, Fujisawa, JP;

Yuji Takeuchi, Yokohama, JP;

Riichiro Shirota, Fujisawa, JP;

Inventors:

Kikuko Sugimae, Yokohama, JP;

Hiroyuki Kutsukake, Yokohama, JP;

Masayuki Ichige, Yokohama, JP;

Michiharu Matsui, Fujisawa, JP;

Yuji Takeuchi, Yokohama, JP;

Riichiro Shirota, Fujisawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.


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