Wafer-level test module for testing image sensor chips, the related test method and fabrication

Abstract

A wafer-level test module is disclosed to include a base layer having multiple first apertures spaced from one another at a pitch corresponding to the pitch of the image sensor chips of an integrated circuit wafer, a cover layer having second apertures respectively axially aimed at the first apertures, and an optical layer sandwiched between the base layer and the cover layer having multiple optical lenses of which the optical axes pass through the first apertures and the second apertures, so that when one image capturing device of the image sensor chips of an integrated circuit wafer is adjusted to the image plane of one of the optical lenses and the wafer-level test module is set in alignment with the integrated circuit wafer horizontally and vertically, then the effective test light can be simultaneously projected onto the image capturing devices of the respective image sensor chips through the wafer-level test module to achieve an effective wafer-level test on multiple image sensor chips of the integrated circuit wafer accurately and rapidly.