The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2008

Filed:

Jan. 10, 2006
Applicant:

Kanta Saino, Tokyo, JP;

Inventor:

Kanta Saino, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/425 (2006.01); H01L 21/8238 (2006.01); H01L 21/3205 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A silicon film is formed on a first region and a second region, respectively of a semiconductor substrate; P-type impurities are selectively ion-implanted into the silicon film in the first region; a first annealing is carried out, thereby the P-type impurities implanted in the silicon film are activated; N-type impurities are selectively ion-implanted into the silicon film in the second region, after the first annealing; a silicide film is formed on the silicon film according to a CVD method, after the ion-implantation of the N-type impurities; a second annealing is carried out, thereby gas contained in the silicide film is discharged and the N-type impurities are activated; a barrier metal film and a metal film are formed in this order on the silicide film; and the metal film, the barrier metal film, the silicide film and the silicon film are patterned, thereby a P-type polymetal gate electrode formed in the first region and an N-type polymetal gate electrode formed in the second region.


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