The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2008

Filed:

Feb. 25, 2005
Applicants:

Xiaodong Zhang, Union City, CA (US);

Jun Kong, San Jose, CA (US);

Bruce W. Mcgaughy, Fremont, CA (US);

Inventors:

Xiaodong Zhang, Union City, CA (US);

Jun Kong, San Jose, CA (US);

Bruce W. McGaughy, Fremont, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A computer implemented method is provided for use in evaluating a hierarchical representation of a circuit design encoded in a computer readable medium comprising: traversing a circuit path within a higher level circuit that includes a reference potential connection, to identify a port of a call to a first lower level circuit that is DC path connected to the reference potential; identifying a first DC port group that includes each port of the call to the first lower level circuit that is DC path connected to the identified port of the call to the first lower level circuit; automatically marking as DC path connected to the reference potential, each port of the call to the first lower level circuit that is a member of the first DC port group; and traversing a circuit path within the first lower level circuit to identify a circuit path within the first lower level circuit that is DC path connected to a marked port of the first lower level circuit.


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