The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2008
Filed:
Jan. 29, 2004
Hideki Yamanaka, Fukushima, JP;
Kiyoshi Demizu, Tokyo, JP;
Tadahiro Ohmi, Aoba-ku, Sendai-shi, Miyagi 980-0813, JP;
Akinobu Teramoto, Sendai, JP;
Shigetoshi Sugawa, Sendai, JP;
Hideki Yamanaka, Fukushima, JP;
Kiyoshi Demizu, Tokyo, JP;
Tadahiro Ohmi, Aoba-ku, Sendai-shi, Miyagi 980-0813, JP;
Akinobu Teramoto, Sendai, JP;
Shigetoshi Sugawa, Sendai, JP;
Shin-Etsu Handotai Co., Ltd., Tokyo, JP;
Other;
Abstract
The present invention has been made in order to manufacture a silicon semiconductor substrate used for a semiconductor integrated circuit device, higher in carrier mobility, especially in electron mobility, which is a carrier of an n-type FET, on a {100} plane as a main surface, and provides a silicon semiconductor substrate and a method for manufacturing the same, wherein the conventional RCA cleaning is employed without the use of special cleaning and the surface of the substrate is planarized at an atomic level to thereby decrease the surface roughness thereof without the use of the radical oxidation. The present invention provides a silicon semiconductor substrate comprising: a {110} plane or a plane inclined from a {110} plane as a main surface of the substrate; and steps arranged at an atomic level along a <110> orientation on the main surface.