The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2008
Filed:
Dec. 26, 2002
Hassan Ihs, Sacramento, CA (US);
Salem Abdennadher, Sacramento, CA (US);
Hassan Ihs, Sacramento, CA (US);
Salem Abdennadher, Sacramento, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
On-chip jitter testing includes providing a clock signal to a circuit under test and delaying outputs from the circuit under test by predetermined delay values. For each delay value, a corresponding output from the circuit under test is compared with a reference signal derived from the clock signal to produce a bit error rate count for each delay value. A jitter value in the output of the circuit under test is determined based on the bit error rate counts.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile