The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2008
Filed:
Jun. 08, 2006
Kanak B. Agarwal, Austin, TX (US);
Ying Liu, Austin, TX (US);
Chandler T. Mcdowell, San Jose, CA (US);
Sani R. Nassif, Austin, TX (US);
James F. Plusquellic, Owing Mills, MD (US);
Jayakumaran Sivagnaname, Austin, TX (US);
Kanak B. Agarwal, Austin, TX (US);
Ying Liu, Austin, TX (US);
Chandler T. McDowell, San Jose, CA (US);
Sani R. Nassif, Austin, TX (US);
James F. Plusquellic, Owing Mills, MD (US);
Jayakumaran Sivagnaname, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.