The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2008
Filed:
Mar. 31, 2006
Louis Bernard Bushard, Rochester, MN (US);
Nathan Paul Chelstrom, Cedar Park, TX (US);
Naoki Kiryu, Machida, JP;
David John Krolak, Rochester, MN (US);
Louis Bernard Bushard, Rochester, MN (US);
Nathan Paul Chelstrom, Cedar Park, TX (US);
Naoki Kiryu, Machida, JP;
David John Krolak, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.