The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2008
Filed:
Mar. 11, 2005
Joachim Deppe, Dresden, DE;
Mathias Krause, Dresden, DE;
Christoph Andreas Kleint, Dresden, DE;
Christoph Ludwig, Langebrück, DE;
Jens-uwe Sachse, Dresden, DE;
Günther Wein, Nittendorf, DE;
Joachim Deppe, Dresden, DE;
Mathias Krause, Dresden, DE;
Christoph Andreas Kleint, Dresden, DE;
Christoph Ludwig, Langebrück, DE;
Jens-Uwe Sachse, Dresden, DE;
Günther Wein, Nittendorf, DE;
Infineon Technology AG, Munich, DE;
Abstract
A non-volatile semiconductor memory () comprising a semiconductor substrate () and a plurality of memory cells () and methods for manufacturing such a memory is provided. Each memory cell () comprises a charge-trapping element (), a gate stack (), nitride spacers () and electrically insulating elements (). The charge-trapping element () is arranged on the semiconductor substrate () and comprises a nitride layer () sandwiched between a bottom oxide layer () and a top oxide layer (), the charge-trapping element () having two lateral sidewalls () opposed to one another. The gate stack () is arranged on top of the charge-trapping element (), the gate stack having two lateral sidewalls () opposing one another. The electrically insulating elements () are disposed at opposing sidewalls () of the charge-trapping element () and cover the sidewalls () of the charge-trapping element (). The nitride spacers () cover the electrically insulating elements () and are arranged on opposing sidewalls () of the gate stack () and on the electrically insulating elements ().