The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7405032 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 29, 2008

Filed:

Aug. 21, 2003
Applicants:

Gilles Amblard, San Jose, CA (US);

Srikanteswara Dakshina-murthy, Wappingers Falls, NY (US);

Bhanwar Singh, Morgan Hill, CA (US);

Inventors:

Gilles Amblard, San Jose, CA (US);

Srikanteswara Dakshina-Murthy, Wappingers Falls, NY (US);

Bhanwar Singh, Morgan Hill, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01B 11/30 (2006.01); G01B 11/00 (2006.01); G03C 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) during gate formation in an integrated circuit. Systems and methods are disclosed for improving critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER, and a trim etch component that facilitates achieving and/or restoring a target critical dimension.


Find Patent Forward Citations

Amblard, Gilles. (2008). Combination of non-lithographic shrink techniques and trim process for gate formation and line-edge roughness reduction (U.S. Patent No. 7405032). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7405032

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