The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2008
Filed:
Oct. 19, 2005
Thomas Mikolajick, Dresden, DE;
Hans Reisinger, Grunwald, DE;
Josef Willer, Riemerling, DE;
Corvin Liaw, München, DE;
Thomas Mikolajick, Dresden, DE;
Hans Reisinger, Grunwald, DE;
Josef Willer, Riemerling, DE;
Corvin Liaw, München, DE;
Infineon Technologies AG, Munich, DE;
Abstract
To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.