The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7402488 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 22, 2008

Filed:

Jun. 23, 2005
Applicants:

Sung-il Cho, Seoul, KR;

Kyeong-koo Chi, Seoul, KR;

Seung-pil Chung, Seoul, KR;

Chang-jin Kang, Suwon-si, KR;

Cheol-kyu Lee, Yongin-si, KR;

Inventors:

Sung-il Cho, Seoul, KR;

Kyeong-koo Chi, Seoul, KR;

Seung-pil Chung, Seoul, KR;

Chang-jin Kang, Suwon-si, KR;

Cheol-kyu Lee, Yongin-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.


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