The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2008
Filed:
Jun. 19, 2006
Applicants:
Hiroshi Yanagigawa, Shiga, JP;
Mitsuru Yoshida, Shiga, JP;
Inventors:
Hiroshi Yanagigawa, Shiga, JP;
Mitsuru Yoshida, Shiga, JP;
Assignee:
NEC Electronics Corporation, Kawasaki, Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/14 (2006.01); H03K 17/284 (2006.01);
U.S. Cl.
CPC ...
Abstract
In a dead time control circuit, a delay circuit is connected to an input terminal and adapted to delay signals therethrough by a delay time corresponding to a dead time. A logic circuit has a first input connected via the delay circuit to the input terminal, a second input connected directly to the input terminal, and an output connected to an output terminal. The dead time having adjustable temperature characteristics.