The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2008
Filed:
Feb. 20, 2003
Anne Gattiker, Austin, TX (US);
David A. Grosch, Burlington, VT (US);
Marc D. Knox, Hinesburg, VT (US);
Franco Motika, Hopewell Junction, NY (US);
Phil Nigh, Williston, VT (US);
Jody Van Horn, Underhill, VT (US);
Paul S. Zuchowski, Jericho, VT (US);
Anne Gattiker, Austin, TX (US);
David A. Grosch, Burlington, VT (US);
Marc D. Knox, Hinesburg, VT (US);
Franco Motika, Hopewell Junction, NY (US);
Phil Nigh, Williston, VT (US);
Jody Van Horn, Underhill, VT (US);
Paul S. Zuchowski, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Methods for testing a semiconductor circuit () including testing the circuit and modifying a well bias () of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control () of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.