The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2008
Filed:
Aug. 04, 2005
Kouichirou Noda, Fukuoka, JP;
Shigenobu Kato, Akiruno, JP;
Goro Kitsukawa, Hinode-machi, JP;
Michihiro Mishima, Kunitachi, JP;
Kouichirou Noda, Fukuoka, JP;
Shigenobu Kato, Akiruno, JP;
Goro Kitsukawa, Hinode-machi, JP;
Michihiro Mishima, Kunitachi, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
There is provided a large capacity memory such as a DRAM and an SDRAM n which bonding pads PS and PD are not located at the center, but are displaced from the center between memory array regions UL and UR, disposed on the upper side of a four-bank structure of banksthrough, and memory array regions DL and DR, disposed on the lower side thereof. Secondly, the disposition of the bonding pads PS and PD is staggered on the right and left such that the right half bonding pads PD are shifted up relative to the left half bonding pads by about 30 μm. Only a sense amplifier, a column decoder and a main amplifier, which need to be near to the memory array regions DL and DR, are disposed between the bonding pads PS and PD, and the lower memory array regions DL and DR, and further indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.