The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2008

Filed:

Mar. 15, 2006
Applicants:

Chang-hyun Lee, Gyeonggi-do, KR;

Jung-dal Choi, Gyeonggi-do, KR;

Chang-seok Kang, Gyeonggi-do, KR;

Yoo-cheol Shin, Gyeonggi-do, KR;

Jong-sun Sel, Gyeonggi-do, KR;

Inventors:

Chang-Hyun Lee, Gyeonggi-do, KR;

Jung-Dal Choi, Gyeonggi-do, KR;

Chang-Seok Kang, Gyeonggi-do, KR;

Yoo-Cheol Shin, Gyeonggi-do, KR;

Jong-Sun Sel, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.


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