The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2008
Filed:
Sep. 30, 2005
James L. Saunders, Mountain View, CA (US);
Krishnan Anandh, San Jose, CA (US);
Guenther Stenz, Campbell, CA (US);
Sudip K. Nag, San Jose, CA (US);
Jason H. Anderson, Toronto, CA;
James L. Saunders, Mountain View, CA (US);
Krishnan Anandh, San Jose, CA (US);
Guenther Stenz, Campbell, CA (US);
Sudip K. Nag, San Jose, CA (US);
Jason H. Anderson, Toronto, CA;
XILINX, Inc., San Jose, CA (US);
Abstract
Method and apparatus are described for a placer system for placing design objects onto an arrayed architecture, such as a programmable logic device including an FPGA. More particularly, a placer interface is described for communicating with a placer core. The placer interface receives information from external entities, and unifies and generalizes this information for the placer core. The external entities comprise different representations of architecture, design, device, constraints and algorithm-dictated placer-movable objects.