The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2008

Filed:

Jan. 18, 2005
Applicants:

Craig E. Hampel, San Jose, CA (US);

Richard E. Perego, San Jose, CA (US);

Stefanos S. Sidiropoulos, Palo Alto, CA (US);

Ely K. Tsern, Los Altos, CA (US);

Fredrick A. Ware, Los Altos Hills, CA (US);

Inventors:

Craig E. Hampel, San Jose, CA (US);

Richard E. Perego, San Jose, CA (US);

Stefanos S. Sidiropoulos, Palo Alto, CA (US);

Ely K. Tsern, Los Altos, CA (US);

Fredrick A. Ware, Los Altos Hills, CA (US);

Assignee:

Rambus Inc., Los Altos, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol. A first circuit of the memory controller receives the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal, and a second circuit of the memory controller receives the second signal by sampling the second symbol using a second timing offset relative to the reference clock signal. The first timing offset is independent of the second timing offset.


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