The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2008
Filed:
Feb. 17, 2004
Norio Suzuki, Mito, JP;
Hiroyuki Ichizoe, Mizuho, JP;
Masayuki Kojima, Kokubunji, JP;
Keiji Okamoto, Higashiyamato, JP;
Shinichi Horibe, Hachiouji, JP;
Kozo Watanabe, Kokubunji, JP;
Yasuko Yoshida, Sayama, JP;
Shuji Ikeda, Koganei, JP;
Akira Takamatsu, Hamura, JP;
Norio Ishitsuka, Chiyoda, JP;
Atsushi Ogishima, Tachikawa, JP;
Maki Shimoda, Hachiouji, JP;
Norio Suzuki, Mito, JP;
Hiroyuki Ichizoe, Mizuho, JP;
Masayuki Kojima, Kokubunji, JP;
Keiji Okamoto, Higashiyamato, JP;
Shinichi Horibe, Hachiouji, JP;
Kozo Watanabe, Kokubunji, JP;
Yasuko Yoshida, Sayama, JP;
Shuji Ikeda, Koganei, JP;
Akira Takamatsu, Hamura, JP;
Norio Ishitsuka, Chiyoda, JP;
Atsushi Ogishima, Tachikawa, JP;
Maki Shimoda, Hachiouji, JP;
Elpida Memory, Inc., Tokyo, JP;
Abstract
A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.