The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2008
Filed:
Mar. 16, 2004
Chandrasekhar Desu, Gresham, OR (US);
Nima A. Behkami, Portland, OR (US);
Bruce J. Whitefield, Camas, WA (US);
David A. Abercrombie, Gresham, OR (US);
David J. Sturtevant, Gresham, OR (US);
ChandraSekhar Desu, Gresham, OR (US);
Nima A. Behkami, Portland, OR (US);
Bruce J. Whitefield, Camas, WA (US);
David A. Abercrombie, Gresham, OR (US);
David J. Sturtevant, Gresham, OR (US);
LSI Corporation, Milpitas, CA (US);
Abstract
A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.